Gate-All-Around (GAA) FET — Going Beyond The 3 Nanometer Mark

An Integrated Circuit (IC) is a set of electronic circuits on one small flat piece (or “chip”) of semiconductor material (normally silicon). The integration of large numbers of tiny MOS (MetalOxide Semiconductor) transistors into a small chip resulted in circuits that are orders of magnitude smaller, faster, and less expensive than those constructed of discrete electronic components. The semiconductor industry has been struggling to maintain the rate of chip performance. As an illustration, devices from companies such as Intel and AMD provide no more than a 10–15% performance boost over the previous generation devices. This makes people familiar with the industry question that has the device performance reached its peak? Will the manufacturers and the designers be able to break the existing performance barriers?

However, it is not easy for the companies that are manufacturing these chips as there are challenges associated with reducing the size of the chips.

Though commonly associated with the decline of Moore’s law, there are several factors that influence performance, increased slowdowns, and semiconductor process node size. As a result of the combined effect of physics, and business goals, the electronics industry is fearing a slowdown in the pace of semiconductor device innovation.

However, not everyone is ready to give up just yet. Samsung, a leader in the semiconductor design business, introduced a significant transistor design called Gate-All-Around, or GAA, that aims to live up to Moore’s law and possibly continue the advancement in transistor-level semiconductor space. Essentially, GAA provides a rework of the traditional transistor design wherein gate material surrounds the silicon semiconductor channel on four sides instead of being covered by the gate from three sides (as used in current FinFET devices). The two primary benefits of this transistor design are reduction in design size, and increased potential for channel length scaling which attributes to increased transistor density.

Figure 1 — Types of FET devices


The first GAAFET was showcased in 1988 by Toshiba which was a vertical nanowire GAAFET, and was called a Surrounding Gate Transistor (SGT). A Gate-All-Around Field Effect Transistor (GAAFET) technology is similar in function to a FinFET transistor but the gate material surrounds the channel from all sides. Generally, based on design, GAAFETs can have two or four gates. Gate-All-Around Field Effect Transistor (GAAFET) technology is believed to be the successor to FinFETs, as it provides better device performance at smaller sizes such as below 7 nm. Nanowire and nanosheet structures are used for the fabrication of GAA transistors. The alignment of the GAAFET structures can be parallel or perpendicular to the substrate depending on the implementation.

Figure 2 — Different FET Structures

Figure 2 highlights the difference between the constructions of different types of FET devices. A FinFET device comprises a fin-like structure made up of silicon that extends from the substrate of the device. One end of the fin acts as a source and the other as a drain of the device. The gate is formed over the fin, contacting the fin on the three sides. This creates a channel within the fin. When compared with a traditional FinFET, the gate contacts the channel formed using nanowires and nanosheets on the four sides, providing better control over the channel characteristics. GAAFET semiconductor device does not feature a fin extending from the substrate instead, the device uses layers of Silicon stacked one over the other with spacing.

Though GAAFET semiconductor devices exhibit better performance than the prior FET designs, the manufacturing of these devices comes with increased complexity. The process of a nanowire GAAFET fabrication starts by growing a superlattice of alternating Si and SiGe epitaxial layers. These layers form the basis for the nanowires and nanosheets. An inner dielectric spacer layer is deposited to conserve the drain and source regions and maintain superior administration over the gate width. The empty spaces between the nanosheets are filled with the gate dielectric material and gate metal.

Figure 3 — FinFET vs GAAFET performance

Figure 3 illustrates the difference in the electrostatic performance of FinFET and nanoribbon GAAFET. The GAAFET device produces a larger drive current at a much lesser supply voltage. The boost in device performance comes in a smaller form factor.


  • With the advent of newer manufacturing processes and the need for efficient devices, the device sizes have become smaller. But, the scaling of transistors brought about intensified short channel effects, leakage due to quantum tunneling, and mobility degradation. FinFETs provided a way to better control the dynamics of the device by introducing a 3-D configuration rather than a planar device. FinFETs were highly scalable due to the design parameters and reduced the leakage currents, and provided faster switching times.
  • The fabrication technology is ever-evolving, and companies had no choice but to switch to FinFETs, but it seems that FinFETs have reached their size thresholds such that reducing the size is getting more difficult and performance improvement is not considerable. The control over leakage current has reduced and the short-channel effects are hampering the operating conditions of the transistor.
  • Current node processing technologies allow the fabrication of 3nm FinFETs. However, with the decreased size, the cost of production has not reduced remarkably.
  • The number and width of the nanosheets can be controlled. This provides engineers better command over the device characteristics such that a wide sheet will drive more current but increase the overall size of the cost. If the producers want they can reduce the device size thereby reducing the drive current. Furthermore, GAA technology has helped to reduce voltage scaling even further which was limited in FinFET due to design restrictions.
  • GAAFET transistors provide greater administration of the gate and make the devices highly efficient. Due to the improved channel dimensions and layout, leakage current is marginal and short-channel effects are inconsequential.

Key Companies Focusing On The GAA Tech

Companies are constantly looking for ways to stay ahead of the competition. This leads to better research and consequently necessary innovation in technology. When it comes to semiconductor fabrication, Samsung, and TSMC are the leading manufacturers of silicon chips.

Samsung Foundry has developed and patented a GAA device of their own, Multi-Bridge Channel FET (MBCFET). MBCFET uses nanosheets stacked on top of each other and allows for more current flow through the stack. MBCFET is compatible with the existing FinFET design flows and manufacturing processes and thus provides enhanced performance without an increase in area.

Figure 4 — Samsung Foundry’s MBCFET with vertically stacked nanosheets

Samsung plans to roll out MBCFET-based devices in 2021 using an in-house 3nm process node, dubbed 3GAE, 3nm Gate-All-Around (GAA) process. 3GAE promises a 45 percent reduction in chip area with 50 percent lower power consumption. The most probable applications of GAAFET (3GAE devices) are in mobile, network, automotive, artificial intelligence (AI), and IoT areas.

Figure 5 — MBCFET device structure

At present, TSMC is busy designing FinFETs at 3nm and is most likely to introduce GAA devices in 2023 since they are behind on the timeline for GAAFET production. TSMC is expected to launch a 2nm TSMC GAAFET node by 2023.

IBM was the company that introduced the term nanosheet to the world. For more than a decade, IBM has been working on GAA technology and played a major role in the evolution of the device architecture from single nanowire to stacked nanosheet. IBM Research’s second-generation nanosheet technology has facilitated the 2-nm node. The new transistor design consists of four gates that enable electrical current to pass efficiently between other transistors on a chip. IBM’s device comprises an inner spacer module that reduces the gate to source/drain capacitance thereby reducing the GAAFET capacitance and intensifying the nanosheet GAAFET performance. Inner spacers are essential because they delineate the gate length. Using the inner spacer, a 12 nm or two dozen atoms long gate length was achieved. This contributed to a reduction in sub-channel leakage, and power-performance improvement.

With FinFET scaling posing a problem for the semiconductor sector, progressively companies will start moving towards the gate-all-around for better performance and gains in production, and become obedient to Moore’s law. It will not come as a surprise if soon manufacturers will start implementing GAAFET tech in all the devices — replacing FinFETs altogether.





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